This invention relates generally to a method for fabricating a semiconductor device, and more specifically to a method for its fabricating an elevated source/drain field effect transistor.
The present day semiconductor integrated circuits include many thousands of semiconductor devices interconnected on a single chip of semiconductor material. As the complexity of the function being integrated increases, more and more devices are packed onto that chip. Additionally, even as the device becomes more complex, the performance of that device often increases also. In order to accommodate the higher packing density and higher performance, each individual device must be reduced in size and particular attention must be paid to reducing parasitic capacitances. At the same time, it is imperative that the process used to fabricate the improved device be both manufacturable and highly reliable.
One device structure which can contribute to reducing both device size and parasitic capacitance is the elevated source/drain structure. In this structure, contact is made to the source and drain regions by a polycrystalline silicon electrode which extends from the source or drain regions themselves up onto the adjoining field insulator. The actual source or drain region can be made small and thus low in capacitance. Electrical contacts to the source and drains usually require the dedication of a relatively large area on the chip, but with the elevated source/drain structure, contact is made by contacting that portion of the polycrystalline silicon electrode which is positioned on the field insulator so that the active area of the device can be minimized.
Although the elevated source/drain structure is recognized as a structure which will achieve many of the proposed size and performance goals, there has not been a reliable and manufacturable process by which such devices can be fabricated.
It is therefore an object of this invention to provide an improved process for the fabrication of semiconductor devices.
It is another object of this invention to provide an improved process for the fabrication of elevated source/drain structures.
It is yet another object of this invention to provide an improved process for the fabrication of advanced submicron CMOS circuits.